Books about Verilog from Amazon.com

- Written for new users. - Explains the language through simple examples - Explains the syntax of language using commonly-used design terminology. - Explains the behavioral style, the dataflow style, and structural style in detail. - Concepts of delay and timing are clearly explained. - Testbench writing is made easier by providing a number of examples. - Many hardware modeling examples have also been provided to make this an excellent reference.

Also includes exercises for every chapter and expanded coverage of more language features including test bench writing strategies.

Third edition is based on IEEE Verilog 2001 Standard. It includes explanations of all the new features introduced in this version of the language, with examples..
Price: $83.25 [Notify me when price goes down.]

Verilog HDL is a language for digital design, just as C is a language for programming This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. This completely updated reference progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis..
Price: $54.99 [Notify me when price goes down.]

Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies.

Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform.

Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers.

Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems.

This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.

.
Price: $67.78 [Notify me when price goes down.]

SystemVerilog language consists of three very specific areas of constructs -- design, assertions and testbench   Assertions add a whole new dimension to the ASIC verification process.  Assertions provide a better way to do verification proactively.  Traditionally, engineers are used to writing verilog test benches that help simulate their design.  Verilog is a procedural language and is very limited in capabilities to handle the complex Asic's built today.  SystemVerilog assertions (SVA) are a declarative and temporal language that provides excellent control over time and parallelism.  This provides the designers a very strong tool to solve their verification problems.  While the language is built solid, the thinking is very different from the user's perspective when compared to standard verilog language.  The concept is still very new and there is not enough expertise in the field to adopt this methodology and be successful.  While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems.  This book will be the practical guide that will help people to understand this new methodology.

"Today's SoC complexity coupled with time-to-market and first-silicon success pressures make assertion based verification a requirement and this book points the way to effective use of assertions."

Satish S. Iyengar, Director, ASIC Engineering, Crimson Microsystems, Inc.

"This book benefits both the beginner and the more advanced users of SystemVerilog Assertions (SVA).  First by introducing the concept of Assertion Based Verification (ABV) in a simple to understand way, then by discussing the myriad of ideas in a broader scope that SVA can accommodate.  The many real life examples, provided throughout the book, are especially useful."

Irwan Sie, Director, IC Design, ESS Technology, Inc.

"SystemVerilog Assertions is a new language that can find and isolate bugs early in the design cycle.  This book shows how to verify complex protocols and memories using SVA with seeral examples.  This book is a good reference guide for both design and verification engineers."

Derick Lin, Senior Director, Engineering, Airgo Networks, Inc.

.
Price: $104.57 [Notify me when price goes down.]

Emphasizing the detailed design of various Verilog projects, Verilog HDL: Digital Design and Modeling offers students a firm foundation on the subject matter. The textbook presents the complete Verilog language by describing different modeling constructs supported by Verilog and by providing numerous design examples and problems in each chapter. Examples include counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and much more. The text also contains information on synchronous and asynchronous sequential machines, including pulse-mode asynchronous sequential machines.

In addition, it provides descriptions of the design module, the test bench module, the outputs obtained from the simulator, and the waveforms obtained from the simulator illustrating the complete functional operation of the design. Where applicable, a detailed review of the topic’s theory is presented together with logic design principles, including state diagrams, Karnaugh maps, equations, and the logic diagram.

Verilog HDL: Digital Design and Modeling is acomprehensive, self-contained, and inclusive textbook that carries all designs through to completion, preparing students to thoroughly understand this popular hardware description language..
Price: $76.76 [Notify me when price goes down.]

This book is intended to help you come up to speed in the design of SystemVerilog transaction-based testbenches that comply with the Verification Methodology Manual (VMM). The goals of this book are to help you adopt, with complete, compilable, and executable examples, the VMM methodology in the creation of comprehensive constrained-random and directed verification environments using a transaction-level modeling (TLM) approach. All code examples are available for download..
Price: $125.00 [Notify me when price goes down.]

The Verilog Programming Language Interface is a powerful feature of the Verilog standard. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired, such as adding custom design debug utilities, adding proprietary file read/write utilities, and interfacing bus functional C language models to a simulator.
This book serves as both a user's guide for learning the Verilog PLI, and as a comprehensive reference manual on the Verilog PLI standard. Both the TF/ACC ("PLI 1.0") and the VPI ("PLI 2.0") generations of the PLI are presented, based on the IEEE 1364 Verilog standard. The second edition of this book adds detailed coverage of the many enhancements added in the latest IEEE 1364-2001 Verilog standard ("Verilog-2001").
A CD is included, with the C source code, Verilog HDL test cases and simulation result logs for more than 75 complete PLI examples..
Price: $134.32 [Notify me when price goes down.]

Fundamentals of Digital Logic With Verilog Design teaches the basic design techniques for logic circuits It emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. Fundamental concepts are illustrated by using small examples.

Use of CAD software is well integrated into the book. A CD-ROM that contains Altera's Quartus CAD software comes free with every copy of the text. The CAD software provides automatic mapping of a design written in Verilog into Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Students will be able to try, firsthand, the book's Verilog examples (over 140) and homework problems.

Engineers use Quartus CAD for designing, simulating, testing and implementing logic circuits. The version included with this text supports all major features of the commercial product and comes with a compiler for the IEEE standard Verilog language. Students will be able to:.

enter a design into the CAD system

compile the design into a selected device

simulate the functionality and timing of the resulting circuit

implement the designs in actual devices (using the school's laboratory facilities).

Verilog is a complex language, so it is introduced gradually in the book. Each Verilog feature is presented as it becomes pertinent for the circuits being discussed. To teach the student to use the Quartus CAD, the book includes three tutorials.. ..
Price: $124.14 [Notify me when price goes down.]

The Designer's Guide to Verilog-AMS presents Verilog-AMS, the new analog and mixed-signal extensions to the widely used Verilog hardware description language.
It starts by describing a rigorous and proven top-down design methodology. Top-down design is widely seen as the key to being able to design very large and complex mixed-signal circuits and it is enabled by Verilog-AMS. Verilog-A and Verilog-AMS are then introduced without assuming that the reader has a background in behavioral modeling. Finally, it includes a comprehensive reference guide for the language.
The Designer's Guide to Verilog-AMS is extensively cross-referenced and indexed, making it an ideal reference for both Verilog-A and Verilog-AMS. A companion website, www.designers-guide.com, provides electronic copies of all the models used in this book, a library of user-contributed models, a discussion forum, additional documents on simulation and modeling, and other useful material.
The Designer's Guide to Verilog-AMS is written for analog and mixed-signal designers, particularly those designing larger and more complex circuits..
Price: $108.00 [Notify me when price goes down.]