Books about Assertion from Amazon.com

SystemVerilog language consists of three very specific areas of constructs -- design, assertions and testbench   Assertions add a whole new dimension to the ASIC verification process.  Assertions provide a better way to do verification proactively.  Traditionally, engineers are used to writing verilog test benches that help simulate their design.  Verilog is a procedural language and is very limited in capabilities to handle the complex Asic's built today.  SystemVerilog assertions (SVA) are a declarative and temporal language that provides excellent control over time and parallelism.  This provides the designers a very strong tool to solve their verification problems.  While the language is built solid, the thinking is very different from the user's perspective when compared to standard verilog language.  The concept is still very new and there is not enough expertise in the field to adopt this methodology and be successful.  While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems.  This book will be the practical guide that will help people to understand this new methodology.

"Today's SoC complexity coupled with time-to-market and first-silicon success pressures make assertion based verification a requirement and this book points the way to effective use of assertions."

Satish S. Iyengar, Director, ASIC Engineering, Crimson Microsystems, Inc.

"This book benefits both the beginner and the more advanced users of SystemVerilog Assertions (SVA).  First by introducing the concept of Assertion Based Verification (ABV) in a simple to understand way, then by discussing the myriad of ideas in a broader scope that SVA can accommodate.  The many real life examples, provided throughout the book, are especially useful."

Irwan Sie, Director, IC Design, ESS Technology, Inc.

"SystemVerilog Assertions is a new language that can find and isolate bugs early in the design cycle.  This book shows how to verify complex protocols and memories using SVA with seeral examples.  This book is a good reference guide for both design and verification engineers."

Derick Lin, Senior Director, Engineering, Airgo Networks, Inc.

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Price: $104.42 [Notify me when price goes down.]

NOTE: Examples in this book can be downloaded from SiMantis Inc. website

BACK-COVER QUOTES:

"This detailed, step-by-step guide provides a thorough introduction to SystemVerilog and the Open Verification Methodology (OVM). With many examples and clear descriptions, it should be helpful to anyone involved in IC functional verification."

Richard Goering, Editor-in-Chief , SCDsource

 

 "Dr. Iman brings together all the essential elements to understand the use and application of OVM. Those with limited SystemVerilog knowledge will find Step-by-Step Functional Verification with SystemVerilog and OVM offers a complete introduction to SystemVerilog, and the SystemVerilog-savvy will find this a comprehensive OVM reference. This book has everything design and verification engineers would want to know to apply OVM to their most pressing challenges."

Dennis Brophy , Director of Strategic Business Development , Mentor Graphics

 

"The author of this book is well known in the design community as a leader in the verification space. SystemVerilog has provided a major step in our capability to verify our designs, especially in today’s world of 40 million gate SoCs. The combination has produced a very thorough step by step guide to the latest in verification methodology."

Gary Smith, Chief Analyst, Gary Smith EDA

 

"The Open Verification Methodology (OVM) is one of the most quickly and widely adopted new solutions ever for verifying complex chips. This book walks the reader through the OVM as well as the SystemVerilog language constructs upon which it is built. The breadth of Step-by-Step Functional Verification with SystemVerilog and OVM and its pragmatic approach make it an invaluable resource for both novice and experienced verification engineers."

Ted Vucurevich, CTO, Cadence

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Price: $139.00 [Notify me when price goes down.]

Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies.

Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform.

Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers.

Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems.

This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.

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Price: $67.78 [Notify me when price goes down.]

This book is intended to help you come up to speed in the design of SystemVerilog transaction-based testbenches that comply with the Verification Methodology Manual (VMM). The goals of this book are to help you adopt, with complete, compilable, and executable examples, the VMM methodology in the creation of comprehensive constrained-random and directed verification environments using a transaction-level modeling (TLM) approach. All code examples are available for download..
Price: $125.00 [Notify me when price goes down.]

A frivolous argument or inflated claim is often dismissed with the reply, "That's just rhetoric!" But as Scott Crider explains in The Office of Assertion, the classical tradition of rhetoric is both a productive and a liberal art. The ability to employ rhetoric successfully can enable the student, as an effective communicator, to reflect qualities of soul through argument. In that sense, rhetoric is much more than a technical skill. Crider addresses the intelligent university student with respect and humor. This short but serious book is informed by both the ancient rhetorical tradition and recent discoveries concerning the writing process. Though practical, it is not simply a "how-to" manual; though philosophical, it never loses sight of writing itself. Crider combines practical guidance about how to improve an academic essay with reflection on the final purposes --educational, political, and philosophical--of such improvement..
Price: $9.18 [Notify me when price goes down.]

SystemVerilog Assertions Handbook is a follow-up book to Using PSL/Sugar for Formal and Dynamic Verification 2nd Edition. It focuses on the assertions aspect of SystemVerilog, along with an explanation of the language concepts along with many examples to demonstrate how SystemVerilog Assertions (SVA) can be effectively used in an Assertion-Based Verification methodology to verify designs written in HDLs like SystemVerilog, Verilog, or VHDL. The integration of assertions in SystemVerilog proves very beneficial for the definition of a verification environment because SystemVerilog is a modern language with powerful and advanced constructs like interfaces, queues, associative array, semaphores, system functions, classes, methods, packages, safe pointers, etc. This book presents different classes of designs, and demonstrates how SystemVerilog Assertions are used in the design process from requirements document, verification plan, design and verification using simulation and formal verification. Many of the examples use the advanced features of SystemVerilog including packages, interfaces, types, and binding. In addition, synthesizable RTL SystemVerilog code examples were synthesized to demonstrated feasibility. Other features provided in this book are a dictionary of English to SystemVerilog Assertions examples, guidelines in the use of SystemVerilog Assertions, and a quick reference guide of the SystemVerilog Assertions syntax. This book represents the collaboration of three authors who are experts in system engineering, architecture, and design and verification with hardware description languages (HDLs) and hardware verification languages (HVLs), along with experience in authoring books, thus bringing more synergism to this SystemVerilog Assertions Handbook..
Price: $150.00 [Notify me when price goes down.]

Learn practical tips and techniques for effective and assertive communication. This easy-to-read book is a practical and valuable resource for anyone who wants to improve their relationship with themselves and with others in their life. Assertiveness is an essential skill to enhance both our work and personal lives and is beneficial in overcoming addictions and other compulsive behaviors. What About Me, What Do I Want? includes:

A discussion of the four styles of communication
How we learn and keep ourselves non-assertive
The role of our self-talk and our beliefs in becoming and staying assertive.
Overcoming our obstacles to being assertive, such as worrying about other's feelings, meeting everyone else's expectations, and the fear of appearing selfish.
Practical tips on how to be assertive, including saying "no", dealing with criticism, letting go of control and consistently expressing our feelings, wants and opinions
Several checklists and self-reflection questions to help you to apply this practical information to your own life


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Price: $15.68 [Notify me when price goes down.]