Books about Nanometer from Amazon.com



Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)

The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction.

Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles. The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions.

Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions. Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

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Price: $74.09 [Notify me when price goes down.]


Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS (The Springer International Series in Engineering and Computer Science)

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level.

The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit.

At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

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Price: $118.77 [Notify me when price goes down.]


Low-Power High-Speed ADCs for Nanometer CMOS Integration (Analog Circuits and Signal Processing) (Analog Circuits and Signal Processing)

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.

1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.

2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash.

3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

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Price: $121.59 [Notify me when price goes down.]


Nanometer CMOS ICs: from Basics to ASICs

CMOS technologies account for almost 90% of all integrated circuits (ICs). This book provides an essential introduction to nanometer CMOS ICs. The contents of this book are based upon several previous publications and editions entitled 'MOS ICs' and 'Deep-Submicron CMOS ICs'.

Nanometer CMOS ICs is fully updated and is not just a copy-and-paste of previous material. It includes aspects of scaling up to and beyond 32nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. In contrast to other works on this topic, the book explores all associated disciplines of nanometer CMOS ICs, including physics, design, technology, yield, packaging, less-power design, variability, reliability and signal integrity. Finally it also includes extensive discussions on the trends and challenges for further scaling. The text is based upon in-house Philips and NXP Semiconductors courseware, which, to date, has been completed by more than 3000 engineers working in a large variety of related disciplines: architecture, design, test, process, packaging, failure analysis and software.

Carefully structured and enriched by in-depth exercises, hundreds of colour figures and photographs and many references, the book is well-suited for the purpose of self-study.

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Price: $173.97 [Notify me when price goes down.]


Inorganic Particle Synthesis via Macro and Microemulsions: A Micrometer to Nanometer Landscape
The present book deals with the most important features of macro-and microemulsions that control the synthesis of inorganic particles of tailored size and shape, followed by wide spectrum surveys of the various procedures as they have been developed by research groups across the world. The aim of this book is thus to open a showcase of basic information on the two chemical regimes and detailed accounts of inorganic particles synthesis using the derived protocols. The intended audience is persons or groups who are not only looking for a simple and focused introduction to these chemical regimes, but also accounts of various synthetic procedures to select from their individual programs. It is also meant for curious individuals who want to know about the basics of the science and the art behind the macro- and microemulsion-based synthesis, but do not find them in a single and simple volume. The significance of this book lies in the fact that it fills this small gap in the immensely large volume of literature on the science and technology of ordinary emulsions and microemulsions..
Price: $90.70 [Notify me when price goes down.]


Nanoscale Calibration Standards and Methods: Dimensional and Related Measurements in the Micro- and Nanometer Range
The quantitative determination of the properties of micro- and nanostructures is essential in research and development It is also a prerequisite in process control and quality assurance in industry. The knowledge of the geometrical dimensions of structures in most cases is the base, to which other physical and chemical properties are linked. Quantitative measurements require reliable and stable instruments, suitable measurement procedures as well as appropriate calibration artefacts and methods. The seminar "NanoScale 2004" (6th Seminar on Quantitative Microscopy and 2nd Seminar on Nanoscale Calibration Standards and Methods) at the National Metrology Institute (Physikalisch-Technische Bundesanstalt PTB), Braunschweig, Germany, continues the series of seminars on Quantitative Microscopy. The series stimulates the exchange of information between manufacturers of relevant hard- and software and the users in science and industry.

Topics addressed in these proceedings are
a) the application of quantitative measurements and measurement problems in: microelectronics, microsystems technology, nano/quantum/molecular electronics, chemistry, biology, medicine, environmental technology, materials science, surface processing
b) calibration & correction methods: calibration methods, calibration standards, calibration procedures, traceable measurements, standardization, uncertainty of measurements
c) instrumentation and methods: novel/improved instruments and methods, reproducible probe/sample positioning, position-measuring systems, novel/improved probe/detector systems, linearization methods, image processing.
Price: $129.00 [Notify me when price goes down.]


Conducting Polymers with Micro or Nanometer Structure

Conducting Polymers with Micro or Nanometer Structure describes a topic discovered by three winners of the Nobel Prize in Chemistry in 2000: Alan J. Heeger, University of California at Santa Barbara, Alan G. MacDiarmid at the University of Pennsylvania, and Hideki Shirakawa at the University of Tsukuba. Since then, the unique properties of conducting polymers have led to promising applications in functional materials and technologies. The book first briefly summarizes the main concepts of conducting polymers before introducing micro/nanostructured conducting polymers dealing with their synthesis, structural characterizations, formation mechanisms, physical and chemical properties, and potential applications in nanomaterials and nanotechnology. The book is intended for researchers in the related fields of chemistry, physics, materials, nanomaterials and nanodevices. Meixiang Wan is a professor at the Institute of Chemistry, Chinese Academy of Sciences, Beijing.

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Price: $161.44 [Notify me when price goes down.]


Putting memory to the test in nanometer designs; memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time ... An article from: EE-Evaluation Engineering
This digital document is an article from EE-Evaluation Engineering, published by Nelson Publishing on October 1, 2004. The length of the article is 2227 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.

Citation Details
Title: Putting memory to the test in nanometer designs; memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time constraints.(Design for Test)
Author: Mark Chadwick
Publication:EE-Evaluation Engineering (Refereed)
Date: October 1, 2004
Publisher: Nelson Publishing
Volume: 43 Issue: 10 Page: 42(4)

Distributed by Thomson Gale.
Price: $5.95 [Notify me when price goes down.]


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